1. Field of the Invention
The present invention relates to a digital processor and a method for controlling the same, and more specifically to a digital signal processor having high performance, and a method for controlling the same.
2. Description of Related Art
In conventional digital processors, generation of addresses is based on an adding operation, and therefore, both of generation for a memory address and an arithmetic and logical operation of data have been performed in common by an arithmetic logic unit (ALU). However, this combined use has become a hindrance in increasing performance. In particular, in a digital signal processor (DSP) in which processings including many repeated processings, such as a sum-of-products operation indispensable for signal processings, are executed, it is important that the address generation is made independently of the arithmetic and logical operation of data, so that the processing is effectively performed.
Recently, Kaneko et al proposed a digital signal processor in "1987 IEEE International Solid-State Circuit Conference", "Digest of Technical Papers", February 1987, pp 158-159, published by IEEE. The proposed digital signal processor includes an address generation circuit composed of an addition circuit having one input connected to an output of an address register, whose input is connected to an output of the addition circuit itself. The other input of the addition circuit is connected to receive through a selector a fixed value "+1", an output of a first displacement register, or an output of a second displacement register. A selection signal for the selector is supplied from a controller within the processor at each operation clock period.
This type of address generation is important in an image processing in which each one pixel is stored at one individual address. Here, consider that a rectangular region is accessed by assuming that the memory has M(=16) pixels in a horizontal direction and N(=20) pixels in a vertical direction and the rectangular region has "m"(=3) pixels in a horizontal direction and "n"(=4) pixels in a vertical direction. If the rectangular region is accessed from an upper left corner, a first horizontal access from the upper left corner to an upper right corner of the rectangular region can be performed by adding "+1" to a current address stored in the address register. Therefore, the selector selects "+1". When the access is moved from the upper right corner to a left end of a second line of the rectangular region, a required address change is obtained by adding {M-(m-1)}(=14) to the current address. Therefore, this displacement value of "14" is previously registered in the first displacement register, and the selector selects this first displacement register. When the access reaches a lower right corner, the address is moved to return to the upper left corner. For this purpose, a required address change is obtained by subtracting {(n-1)M+(m-1)}(=50) from the current address. Therefore, this displacement value of "-50" is previously registered in the second displacement register, and the selector selects this second displacement register. Thus, a triple loop processing is performed.
For the loop processing, the number of loops and the end discrimination are described in a program, and the controller decodes the program at each step so as to supply a necessary selection signal to the selector.
In the above mentioned digital processor and the controlling method therefor, if the number of the memories to be accessed simultaneously becomes large, a corresponding number of selection signals must be simultaneously supplied. For elevation of the processing capacity of the processor, it can be sufficiently considered that a simultaneous access to a number of memories is required. However, a controller of many processors is configured so that a so-called horizontal microinstruction is read out at each operation clock period, and then decoded to generate various control signals including the selection signal, so that the various control signals are supplied to different parts of the processor. Therefore, in order to simultaneously supply a number of selection signals, it is necessary to elongate each one microinstruction, which means that it is required to increase the capacity of a microprogram memory storing the microinstructions. This will result in a decreased reading speed and in an increased cost.
In addition, in order to improve the operation clock period, it may become necessary to cause various circuits of the processor including the ALU to operate in a pipeline mode. In this case, because of the number of pipelined steps, the loop processing for generating an address for the memory supplying the data to the ALU and the loop processing for generating an address for the memory storing the result of the operation of the ALU must be executed with a time difference therebetween. However, the two loop processings (or more than two loop processings in some cases) having a time difference from each other cannot be controlled in the conventional manner in which one microinstruction is read out for each one clock period and decoded to perform a necessary processing.